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| (R) UCT T MEN PROD ETE REPLACE nter at OL OBS NDED rt Ce m/tsc ME uppo COM chnical S intersil.co E . December 1995, Rev. E NO R Data e ur T Sheet ww w act o RSIL or ont NTE c -I 1-888 EL2072 FN7033 730MHz Closed Loop Buffer The EL2072 is a wide bandwidth, fast settling monolithic buffer built using an advanced complementary bipolar process. This buffer is closed loop to achieve lower output impedance and higher gain accuracy. Designed for closedloop unity gain, the EL2072 has a 730MHz -3dB bandwidth and 5ns settling to 0.2% while consuming only 15mA of supply current. The EL2072 is an obvious high-performance solution for video distribution and line-driving applications. With low 15mA supply current and a 70mA output drive, performance in these areas is assured. The EL2072's settling to 0.2% in 5ns, low distortion, and ability to drive capacitive loads make it an ideal flash A/D driver. The wide 730MHz bandwidth and extremely linear phase allow unmatched signal fidelity. The EL2072 can be used inside an amplifier loop or PLL as its wide bandwidth and fast rise time have minimal effect on loop dynamics. Elantec products and facilities comply with MIL-I-45028A, and other applicable quality specifications. For information on Elantec's processing, see Elantec document QRA-1: Elantec's Processing, Monolithic Integrated Circuits. Features * 730MHz -3dB bandwidth (0.5VPP) * 5ns settling to 0.2% * VS = 5V @ 15mA * Low distortion: HD2, HD3 of -65dBc at 20MHz * Overload/short-circuit protected * Closed-loop, unity gain * Low cost * Direct replacement for CLC110 Applications * Video buffer * Video distribution * HDTV buffer * High-speed A/D buffer * Photodiode, CCD preamps * IF processors * High-speed communications Ordering Information PART NUMBER EL2072CN TEMP. RANGE -40C to +85C -40C to +85C PACKAGE 8-Pin PDIP 8-Pin SO PKG. NO. MDP0031 MDP0027 Pinout EL2072 (8-PIN PDIP SO) TOP VIEW EL2072CS Manufactured under U.S. Patent No. 4,893,091 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2003. All Rights Reserved. Elantec is a registered trademark of Elantec Semiconductor, Inc. All other trademarks mentioned are the property of their respective owners. EL2072 Absolute Maximum Ratings (TA = 25C) Supply Voltage (VS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7V Output Current Output is short-circuit protected to ground, however, maximum reliability is obtained if IOUT does not exceed 70mA. Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VS Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40C to +85C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-60C to +150C Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . .JA = 95C/W PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . JA = 175C/W SO Note: See EL2071/EL2171 for Thermal Impedance curves. CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA DC Electrical Specifications PARAMETER VOS Output Offset Voltage VS = 5V, RL = 100, RS = 50 unless otherwise specified TEST CONDITIONS TEMP 25C TMIN TMAX MIN TYP 2.0 MAX 8.0 16.0 13.0 20.0 20.0 10.0 50.0 100.0 50.0 100.0 200.0 200.0 0.96 0.95 0.2 0.4 0.8 0.3 45.0 65.0 15.0 100.0 50.0 200.0 1.6 2.2 2.5 2.0 3.0 3.5 50.0 45.0 3.2 3.0 4.0 70.0 160.0 20.0 0.98 300.0 700.0 V/V V/V %F.S. %F.S. %F.S. dB mA k k k pF pF mA mA V V A A nA/C UNITS mV mV mV V/C DESCRIPTION TCVOS Average Offset Voltage Drift 25C - TMAX 25C - TMIN IB Input Bias Current 25C, TMAX TMIN TCIB Average Input Bias Current Drift 25C - TMAX 25C - TMIN AV Small Signal Gain RL = 100 25C TMIN, TMAX ILIN Integral End Point linearity 2V F.S. 25C TMIN TMAX PSRR IS RIN Power Supply Rejection Ratio Supply Current--Quiescent Input Resistance No Load All All 25C TMIN TMAX CIN Input Capacitance 25C TMIN, TMAX ROUT Output Impedance (DC) 25C TMIN, TMAX IOUT Output Current 25C, TMAX TMIN VOUT Output Voltage Swing RL = 100 25C, TMAX TMIN 2 EL2072 AC Electrical Specifications PARAMETER FREQUENCY RESPONSE SSBW -3dB Bandwidth (VOUT < 0.5VPP) 25C TMIN TMAX LSBW -3dB Bandwidth (VOUT = 5.0VPP) 25C TMIN, TMAX 400.0 400.0 300.0 55.0 50.0 90.0 730.0 MHz MHz MHz MHz MHz VS = 5V, RL = 100, RS = 50 unless otherwise specified TEST CONDITIONS TEMP MIN TYP MAX UNITS DESCRIPTION GAIN FLATNESS GFPL Peaking VOUT < 0.5VPP < 200MHz 25C TMAX TMIN GFR Rolloff VOUT < 0.5VPP < 200MHz 25C TMIN TMAX GDL Group Delay < 200MHz 25C, TMIN TMAX LPD Linear Phase Deviation VOUT < 0.5VPP < 200MHz 25C, TMIN TMAX 0.7 0.75 0.0 0.0 0.5 0.6 0.8 0.8 1.0 1.2 1.0 1.2 1.5 2.0 dB dB dB dB dB dB ns ns TIME-DOMAIN RESPONSE TR1, TF1 Rise Time, Fall Time Input Signal Rise/Fall = 300ps Rise Time, Fall Time Input Signal Rise/Fall 1ns Settling Time to 0.2% Input Signal Rise/Fall 1ns Overshoot Input Signal Rise/Fall = 300ps Slew Rate 0.5V Step 25C, TMIN TMAX 5.0V Step 25C TMIN, TMAX 2.0V Step All 5.0 4.5 0.4 1.0 1.4 7.5 8.5 10.0 ns ns ns ns ns TR2, TF2 TS1 OS 0.5V Step 25C TMIN, TMAX 25C TMIN, TMAX 500.0 450.0 0.0 10.0 15.0 % % V/s V/s SR 800.0 DISTORTION HD2 2nd Harmonic Distortion at 20MHz 2VPP 25C TMIN TMAX HD2A 2nd Harmonic Distortion at 50MHz 3rd Harmonic Distortion at 20MHz 3rd Harmonic Distortion at 50MHz 2VPP 25C, TMAX TMIN 2VPP 25C TMIN, TMAX 2VPP 25C, TMIN TMAX -60.0 -65.0 -50.0 -55.0 -50.0 -48.0 -55.0 -45.0 -40.0 -55.0 -55.0 -50.0 -45.0 dBc dBc dBc dBc dBc dBc dBc dBc dBc HD3 HD3A 3 EL2072 AC Electrical Specifications PARAMETER VS = 5V, RL = 100, RS = 50 unless otherwise specified (Continued) TEST CONDITIONS TEMP MIN TYP MAX UNITS DESCRIPTION EQUIVALENT INPUT NOISE NF Noise Floor > 100kHz Integrated Noise 100kHz to 200MHz 25C, TMIN TMAX 25C, TMIN TMAX 40.0 -158.0 -155.0 -154.0 57.0 63.0 dBm (1Hz) dBm (1Hz) V V INV 4 EL2072 Typical Performance Curves Forward Gain and Phase Gain Flatness & Deviation from Linear Phase Reverse Gain and phase Input Impedance Output Impedance Recommended RS vs Load Capacitance Integral Linearity Error Frequency Response vs RLOAD |S21| vs CLOAD with Recommended Rs Small Signal Pulse Response Large Signal Pulse Response Long-Term Settling Time 2nd Harmonic Distortion 3rd Harmonic Distortion 2-Tone, 3rd Order Intermodulation Intercept 5 EL2072 Burn-In Circuit Printed Circuit Layout As with any high-frequency device, good PCB layout is necessary for optimum performance. This is especially important for the EL2072, which has a typical bandwidth of 730MHz. Ground plane construction is a requirement, as is good power-supply bypassing close to the package. A closely-placed 0.01F ceramic capacitor between each supply pin and the ground plane is usually sufficient decoupling. Pins 2, 3, 6, and 7 should be connected to the ground-plane to minimize capacitive feedthrough, and all input and output traces should be laid out as transmission lines and terminated as close to the EL2072 package as possible. Increasing capacitance on the output of the EL2072 will add phase shift, decreasing phase margin and increasing frequency-response peaking. A small series resistor before the capacitance decouples this effect, and should be used for large capacitance values. Please refer to the graphs for the appropriate resistor value to be used. All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com 6 |
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